Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura. An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 557-566, IEEE, 2006. [doi]
@inproceedings{FujisawaKKNRNFY06,
title = {An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme},
author = {Hiroki Fujisawa and Shuichi Kubouchi and Koji Kuroki and Naohisa Nishioka and Yoshiro Riho and Hiromasa Noda and Isamu Fujii and Hideyuki Yoko and Ryuuji Takishita and Takahiro Ito and Hitoshi Tanaka and Masayuki Nakamura},
year = {2006},
doi = {10.1109/ISSCC.2006.1696092},
url = {https://doi.org/10.1109/ISSCC.2006.1696092},
researchr = {https://researchr.org/publication/FujisawaKKNRNFY06},
cites = {0},
citedby = {0},
pages = {557-566},
booktitle = {2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006},
publisher = {IEEE},
isbn = {1-4244-0079-1},
}