Synthesizing Verification Aware Models: Why and How?

Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi. Synthesizing Verification Aware Models: Why and How?. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 50-56, IEEE Computer Society, 2007. [doi]

Abstract

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