Joel W. Gannett. SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts. IEEE Trans. on CAD of Integrated Circuits and Systems, 9(6):669-674, 1990. [doi]
@article{Gannett90,
title = {SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts},
author = {Joel W. Gannett},
year = {1990},
doi = {10.1109/43.55197},
url = {http://doi.ieeecomputersociety.org/10.1109/43.55197},
tags = {layout},
researchr = {https://researchr.org/publication/Gannett90},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {9},
number = {6},
pages = {669-674},
}