Mario Garrido. Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal. IEEE Trans. on Circuits and Systems, 66-II(4):657-661, 2019. [doi]
@article{Garrido19,
title = {Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal},
author = {Mario Garrido},
year = {2019},
doi = {10.1109/TCSII.2018.2880921},
url = {https://doi.org/10.1109/TCSII.2018.2880921},
researchr = {https://researchr.org/publication/Garrido19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {66-II},
number = {4},
pages = {657-661},
}