Xiang Ge, Hengliang Zhu, Fan Yang 0001, Lingli Wang, Xuan Zeng 0001. Parallel sparse LU decomposition using FPGA with an efficient cache architecture. In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 259-262, IEEE, 2017. [doi]
Abstract is missing.