Fault modeling and testing of through silicon via interconnections

Vasileios Gerakis, Leonidas Katselas, Alkis A. Hatzopoulos. Fault modeling and testing of through silicon via interconnections. In 21st IEEE International On-Line Testing Symposium, IOLTS 2015, Halkidiki, Greece, July 6-8, 2015. pages 30-31, IEEE, 2015. [doi]

@inproceedings{GerakisKH15,
  title = {Fault modeling and testing of through silicon via interconnections},
  author = {Vasileios Gerakis and Leonidas Katselas and Alkis A. Hatzopoulos},
  year = {2015},
  doi = {10.1109/IOLTS.2015.7229824},
  url = {http://dx.doi.org/10.1109/IOLTS.2015.7229824},
  researchr = {https://researchr.org/publication/GerakisKH15},
  cites = {0},
  citedby = {0},
  pages = {30-31},
  booktitle = {21st IEEE International On-Line Testing Symposium, IOLTS 2015, Halkidiki, Greece, July 6-8, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-7905-2},
}