Gianfranco Gerosa, Mike Alexander, Jose Alvarez, Cody Croxton, Michael D'Addeo, A. Richard Kennedy, Carmine Nicoletta, James P. Nissen, Ross Philip, Paul Reed, Hector Sanchez, Scott A. Taylor, Brad Burgess. A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller. J. Solid-State Circuits, 32(11):1635-1649, 1997. [doi]
@article{GerosaAACDKNNPR97,
title = {A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller},
author = {Gianfranco Gerosa and Mike Alexander and Jose Alvarez and Cody Croxton and Michael D'Addeo and A. Richard Kennedy and Carmine Nicoletta and James P. Nissen and Ross Philip and Paul Reed and Hector Sanchez and Scott A. Taylor and Brad Burgess},
year = {1997},
doi = {10.1109/4.641684},
url = {https://doi.org/10.1109/4.641684},
researchr = {https://researchr.org/publication/GerosaAACDKNNPR97},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {32},
number = {11},
pages = {1635-1649},
}