G. Ghidini, A. Garavaglia, G. Giusto, A. Ghetti, R. Bottini, D. Peschiaroli, M. Scaravaggi, F. Cazzaniga, D. Ielmini. Impact of gate stack process on conduction and reliability of 0.18 mum PMOSFET. Microelectronics Reliability, 43(8):1221-1227, 2003. [doi]
@article{GhidiniGGGBPSCI03,
title = {Impact of gate stack process on conduction and reliability of 0.18 mum PMOSFET},
author = {G. Ghidini and A. Garavaglia and G. Giusto and A. Ghetti and R. Bottini and D. Peschiaroli and M. Scaravaggi and F. Cazzaniga and D. Ielmini},
year = {2003},
doi = {10.1016/S0026-2714(03)00175-6},
url = {http://dx.doi.org/10.1016/S0026-2714(03)00175-6},
tags = {reliability},
researchr = {https://researchr.org/publication/GhidiniGGGBPSCI03},
cites = {0},
citedby = {0},
journal = {Microelectronics Reliability},
volume = {43},
number = {8},
pages = {1221-1227},
}