Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses

Maged Ghoneima, Yehea I. Ismail. Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. In Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy, editors, Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004. pages 66-69, ACM, 2004. [doi]

Abstract

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