Table of Contents

• Why hot chips are no longer cool Ray Bryant. 1 [doi]
• Leakage power reduction by dual-vth designs under probabilistic analysis of vth variationMichael Liu, Wei-Shen Wang, Michael Orshansky. 2-7 [doi]
• Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOSHari Ananthan, Chris H. Kim, Kaushik Roy. 8-13 [doi]
• Technology exploration for adaptive power and frequency scaling in 90nm CMOSMaurice Meijer, Francesco Pessolano, José Pineda de Gyvez. 14-19 [doi]
• Experimental measurement of a novel power gating structure with intermediate power saving modeSuhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin G. Stawiasz. 20-25 [doi]
• Improved clock-gating through transparent pipeliningHans M. Jacobson. 26-31 [doi]
• Microarchitectural techniques for power gating of execution unitsZhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose. 32-37 [doi]
• SEPAS: a highly accurate energy-efficient branch predictorAmirali Baniasadi, Andreas Moshovos. 38-43 [doi]
• Understanding the energy efficiency of simultaneous multithreadingYingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose. 44-49 [doi]
• Impact of technology scaling on energy aware execution cache-based microarchitecturesEmil Talpes, Diana Marculescu. 50-53 [doi]
• Design and implementation of correlating cachesArindam Mallik, Matthew C. Wildrick, Gokhan Memik. 58-61 [doi]
• Dynamic power management for streaming dataNathaniel Pettis, Le Cai, Yung-Hsiang Lu. 62-65 [doi]
• Delayed line bus scheme: a low-power bus scheme for coupled on-chip busesMaged Ghoneima, Yehea I. Ismail. 66-69 [doi]
• Delay optimal low-power circuit clustering for FPGAs with dual supply voltagesDeming Chen, Jason Cong. 70-73 [doi]
• Creating a power-aware structured ASICR. Reed Taylor, Herman Schmit. 74-77 [doi]
• Dynamic voltage scaling for systemwide energy minimization in real-time embedded systemsRavindra Jejurikar, Rajesh K. Gupta. 78-81 [doi]
• ESACW: an adaptive algorithm for transmission power reduction in wireless networksHang Su, Peiliang Qiu, Qinru Qiu. 82-85 [doi]
• Any-time probabilistic switching model using bayesian networksShiva Shankar Ramani, Sanjukta Bhanja. 86-89 [doi]
• Characterizing and modeling minimum energy operation for subthreshold circuitsBenton H. Calhoun, Anantha Chandrakasan. 90-95 [doi]
• Device optimization for ultra-low power digital sub-threshold operationBipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy. 96-101 [doi]
• Nanoscale CMOS circuit leakage power reduction by double-gate deviceKeunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang. 102-107 [doi]
• 4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensorsStefanos Kaxiras, Polychronis Xekalakis. 108-113 [doi]
• HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reductionChia-Lin Yang, Chien-Hao Lee. 114-119 [doi]
• Location cache: a low-power L2 cache systemRui Min, Wen-Ben Jone, Yiming Hu. 120-125 [doi]
• A way-halting cache for low-energy high-performance systemsChuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. 126-131 [doi]
• Soft error and energy consumption interactions: a data cache perspectiveLin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 132-137 [doi]
• Post-layout leakage power minimization based on distributed sleep transistor insertionPietro Babighian, Luca Benini, Alberto Macii, Enrico Macii. 138-143 [doi]
• Active mode leakage reduction using fine-grained forward body biasing strategyVishal Khandelwal, Ankur Srivastava. 150-155 [doi]
• A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variationsSongqing Zhang, Vineet Wason, Kaustav Banerjee. 156-161 [doi]
• Maximizing efficiency of solar-powered systems by load matchingDexin Li, Pai H. Chou. 162-167 [doi]
• Power utility maximization for multiple-supply systems by a load-matching switchChulsung Park, Pai H. Chou. 168-173 [doi]
• Dynamic voltage and frequency scaling based on workload decompositionKihwan Choi, Ramakrishna Soma, Massoud Pedram. 174-179 [doi]
• Architecting voltage islands in core-based system-on-a-chip designsJingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu Marculescu. 180-185 [doi]
• Balanced energy optimizationJohn Cornish. 186 [doi]
• Battery life challenges on future mobile notebook platformsShreekant (Ticky) Thakkar. 187 [doi]
• Approaches to run-time and standby mode leakage reduction in global busesRahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif. 188-193 [doi]
• Spatial encoding circuit techniques for peak power reduction of on-chip high-performance busesHimanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy. 194-199 [doi]
• A new algorithm for improved VDD assignment in low power dual VDD systemsSarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester. 200-205 [doi]
• Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfacesSabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino. 206-211 [doi]
• Microarchitectural power modeling techniques for deep sub-micron microprocessorsNam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M. Austin, Trevor N. Mudge. 212-217 [doi]
• Power-optimal pipelining in deep submicron technologySeongmoo Heo, Krste Asanovic. 218-223 [doi]
• Application-level prediction of battery dissipationChandra Krintz, Ye Wen, Richard Wolski. 224-229 [doi]
• Minimizing power consumption and complexity in a programmable transmit filter bank for OFDMAlireza Mehrnia, Babak Daneshrad. 230-235 [doi]
• On optimality of adiabatic switching in MOS energy-recovery circuitBaohua Wang, Pinaki Mazumder. 236-239 [doi]
• Constant-load energy recovery memory for efficient high-speed operationJoohee Kim, Marios C. Papaefthymiou. 240-243 [doi]
• A comparative study of MOS VCOs for low voltage high performance operationJing-Hong Conan Zhan, Jon S. Duster, Kevin T. Kornegay. 244-247 [doi]
• A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologiesBhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy. 248-251 [doi]
• A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approachHui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu. 252-256 [doi]
• Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulationChuang Zhang, Dongsheng Ma, Ashok Srivastava. 257-262 [doi]
• Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generationGerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De. 263-268 [doi]
• 2.45 GHz power and data transmission for a low-power autonomous sensors platformStefano Gregori, Yunlei Li, Huijuan Li, Jin Liu, Franco Maloberti. 269-273 [doi]
• Managing standby and active mode leakage power in deep sub-micron designLawrence T. Clark, Rakesh Patel, Timothy S. Beatty. 274-279 [doi]
• Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10MbpsMarian Verhelst, Wim Vereecken, Michiel Steyaert, Wim Dehaene. 280-285 [doi]
• Low-power asynchronous viterbi decoder for wireless applicationsMohamed Kawokgy, C. Andre T. Salama. 286-289 [doi]
• A CMOS even harmonic mixer with current reuse for low power applicationsMing-Feng Huang, Shuenn-Yuh Lee, Chung J. Kuo. 290-295 [doi]
• A novel continuous-time common-mode feedback for low-voltage switched-OPAMPM. Ali-Bakhshian, K. Sadeghi. 296-300 [doi]
• The design of a low power asynchronous multiplierYijun Liu, Stephen B. Furber. 301-306 [doi]
• Low-power fixed-width array multipliersJinn-Shyan Wang, Chien-Nan Kuo, Tsung-Han Yang. 307-312 [doi]
• Low-power carry-select adder using adaptive supply voltage based on input vector patternsHiroaki Suzuki, Woopyo Jeong, Kaushik Roy. 313-318 [doi]
• Reducing pipeline energy demands with local DVS and dynamic retimingSeokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge. 319-324 [doi]
• Understanding nanoscale conductorsSupriyo Datta. 325 [doi]
• Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimizationKim M. Hazelwood, David Brooks. 326-331 [doi]
• On optimality of adiabatic switching in MOS energy-recovery circuitBaohua Wang, Pinaki Mazumder. 332-337 [doi]
• Energy-aware demand paging on NAND flash-based embedded storagesChanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jinsoo Kim. 338-343 [doi]
• Application adaptive energy efficient clustered architecturesDiana Marculescu. 344-349 [doi]
• The impact of variability on powerSani R. Nassif. 350 [doi]
• Reducing radio energy consumption of key management protocols for wireless sensor networksBo-Cheng Lai, David Hwang, Sungha Pete Kim, Ingrid Verbauwhede. 351-356 [doi]
• Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systemsFeng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min. 357-362 [doi]
• Experience with a low power wireless mobile computing platformVijay Raghunathan, Trevor Pering, Roy Want, Alex Nguyen, Peter Jensen. 363-368 [doi]
• FSM--based power modeling of wireless protocols: the case of bluetoothLuca Negri, Mariagiovanna Sami, David Macii, Alessandra Terranegra. 369-374 [doi]
• Efficient adaptive voltage scaling system through on-chip critical path emulationMohamed Elgebaly, Manoj Sachdev. 375-380 [doi]
• An efficient voltage scaling algorithm for complex SoCs with few number of voltage modesBita Gorjiara, Nader Bagherzadeh, Pai H. Chou. 381-386 [doi]
• Memory-aware energy-optimal frequency assignment for dynamic supply voltage scalingYoungjin Cho, Naehyuck Chang. 387-392 [doi]
• Preemption-aware dynamic voltage scaling in hard real-time systemsWoonseok Kim, Jihong Kim, Sang Lyul Min. 393-398 [doi]