Low-power on-chip bus architecture using dynamic relative delays

Maged Ghoneima, Yehea I. Ismail. Low-power on-chip bus architecture using dynamic relative delays. In Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA. pages 233-236, IEEE, 2004. [doi]

Authors

Maged Ghoneima

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Yehea I. Ismail

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