Prokash Ghosh, Jyotirmoy Ghosh. A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC. In Brajesh Kumar Kaushik, Sudeb Dasgupta, Virendra Singh, editors, VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers. Volume 711 of Communications in Computer and Information Science, pages 619-627, Springer, 2017. [doi]
@inproceedings{GhoshG17-2,
title = {A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC},
author = {Prokash Ghosh and Jyotirmoy Ghosh},
year = {2017},
doi = {10.1007/978-981-10-7470-7_59},
url = {https://doi.org/10.1007/978-981-10-7470-7_59},
researchr = {https://researchr.org/publication/GhoshG17-2},
cites = {0},
citedby = {0},
pages = {619-627},
booktitle = {VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
editor = {Brajesh Kumar Kaushik and Sudeb Dasgupta and Virendra Singh},
volume = {711},
series = {Communications in Computer and Information Science},
publisher = {Springer},
isbn = {978-981-10-7470-7},
}