Pavel Ghosh, Arunabha Sen. Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010. pages 654-657, IEEE, 2010. [doi]
@inproceedings{GhoshS10,
title = {Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective},
author = {Pavel Ghosh and Arunabha Sen},
year = {2010},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5457124},
researchr = {https://researchr.org/publication/GhoshS10},
cites = {0},
citedby = {0},
pages = {654-657},
booktitle = {Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010},
publisher = {IEEE},
}