Static Timing Analysis of Asynchronous Bundled-Data Circuits

Gregoire Gimenez, Abdelkarim Cherkaoui, Guillaume Cogniard, Laurent Fesquet. Static Timing Analysis of Asynchronous Bundled-Data Circuits. In 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018. pages 110-118, IEEE Computer Society, 2018. [doi]

@inproceedings{GimenezCCF18,
  title = {Static Timing Analysis of Asynchronous Bundled-Data Circuits},
  author = {Gregoire Gimenez and Abdelkarim Cherkaoui and Guillaume Cogniard and Laurent Fesquet},
  year = {2018},
  doi = {10.1109/ASYNC.2018.00036},
  url = {https://doi.org/10.1109/ASYNC.2018.00036},
  researchr = {https://researchr.org/publication/GimenezCCF18},
  cites = {0},
  citedby = {0},
  pages = {110-118},
  booktitle = {24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5386-5883-3},
}