Verilog-a modeling of Silicon Photo-Multipliers

Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo. Verilog-a modeling of Silicon Photo-Multipliers. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 1270-1273, IEEE, 2016. [doi]

Authors

Gianluca Giustolisi

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Gaetano Palumbo

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Paolo Finocchiaro

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Alfio Pappalardo

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