Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang. A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. In VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015. pages 1-4, IEEE, 2015. [doi]
@inproceedings{GohLC15,
title = {A dual-edge sampling CES delay-locked loop based clock and data recovery circuits},
author = {Jih Ren Goh and Yen-Long Lee and Soon-Jyh Chang},
year = {2015},
doi = {10.1109/VLSI-DAT.2015.7114500},
url = {http://dx.doi.org/10.1109/VLSI-DAT.2015.7114500},
researchr = {https://researchr.org/publication/GohLC15},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015},
publisher = {IEEE},
isbn = {978-1-4799-6275-4},
}