A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Jih Ren Goh, Yen-Long Lee, Soon-Jyh Chang. A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. In VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015. pages 1-4, IEEE, 2015. [doi]

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