A low-power 2-GSample/s comparator in 120 nm CMOS technology

Bernard Goll, Horst Zimmermann. A low-power 2-GSample/s comparator in 120 nm CMOS technology. In Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët, editors, Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005. pages 507-510, IEEE, 2005. [doi]

Abstract

Abstract is missing.