FPGA latency optimization using system-level transformations and DFG restructuring - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier. FPGA latency optimization using system-level transformations and DFG restructuring. In Enrico Macii, editor, Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. pages 1553-1558, EDA Consortium San Jose, CA, USA / ACM DL, 2013. [doi]

This author has not been identified. Look up 'Daniel Gomez-Prado' in GoogleThis author has not been identified. Look up 'Maciej J. Ciesielski' in GoogleThis author has not been identified. Look up 'Russell Tessier' in Google

runs on WebDSL