Sub-picosecond-jitter clock generation for interleaved ADC with Delay-Locked-Loop in 28nm CMOS - researchr publication

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Jianping Gong, Sulin Li, John A. McNeill. Sub-picosecond-jitter clock generation for interleaved ADC with Delay-Locked-Loop in 28nm CMOS. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 2763-2766, IEEE, 2016. [doi]

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