A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture

Wenqiang Gong, Fang Zhou 0001, Fen Ge. A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture. In 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023. pages 1-5, IEEE, 2023. [doi]

Abstract

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