Marcel Gort, Jason Helge Anderson. Reducing FPGA Router Run-Time through Algorithm and Architecture. In International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece. pages 336-342, IEEE, 2011. [doi]
@inproceedings{GortA11,
title = {Reducing FPGA Router Run-Time through Algorithm and Architecture},
author = {Marcel Gort and Jason Helge Anderson},
year = {2011},
doi = {10.1109/FPL.2011.67},
url = {http://doi.ieeecomputersociety.org/10.1109/FPL.2011.67},
researchr = {https://researchr.org/publication/GortA11},
cites = {0},
citedby = {0},
pages = {336-342},
booktitle = {International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece},
publisher = {IEEE},
isbn = {978-1-4577-1484-9},
}