Prema Kumar Govindaswamy, Mursina Khatun, Vijay Shankar Pasupureddi. A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS. In 25th International Symposium on Quality Electronic Design, ISQED 2024, San Francisco, CA, USA, April 3-5, 2024. pages 1-5, IEEE, 2024. [doi]
Abstract is missing.