Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa. Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. In 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 7-10, 2011. pages 310-317, IEEE, 2011. [doi]
Abstract is missing.