Abstract is missing.
- Keynote address: Design of secure systems - Where are the EDA tools?Georg Sigl. 1 [doi]
- Layout decomposition for triple patterning lithographyBei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan. 1-8 [doi]
- Optimal layout decomposition for double patterning technologyXiaoping Tang, Minsik Cho. 9-13 [doi]
- A framework for double patterning-enabled designRani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta. 14-20 [doi]
- Unequal-error-protection codes in SRAMs for mobile multimedia applicationsXuebei Yang, Kartik Mohanram. 21-27 [doi]
- Detecting stability faults in sub-threshold SRAMsChen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao. 28-33 [doi]
- Pseudo-functional testing for small delay defects considering power supply noise effectsFeng Yuan, Xiao Liu, Qiang Xu. 34-39 [doi]
- A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video CodingBruno Zatt, Muhammad Shafique, Sergio Bampi, Jörg Henkel. 40-47 [doi]
- Bandwidth-aware reconfigurable cache design with hybrid memory technologiesJishen Zhao, Cong Xu, Yuan Xie. 48-55 [doi]
- Feedback control based cache reliability enhancement for emerging multicoresHui Zhao, Akbar Sharifi, Shekhar Srikantaiah, Mahmut T. Kandemir. 56-62 [doi]
- GPU programming for EDA with OpenCLRasit Onur Topaloglu, Benedict R. Gaster. 63-66 [doi]
- A SimPLR method for routability-driven placementMyung-Chul Kim, Jin Hu, DongJin Lee, Igor L. Markov. 67-73 [doi]
- Ripple: An effective routability-driven placer by iterative cell movementXu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young. 74-79 [doi]
- Routability-driven analytical placement for mixed-size circuit designsMeng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang. 80-84 [doi]
- PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designsYi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu. 85-90 [doi]
- Efficient analytical macromodeling of large analog circuits by Transfer Function TrajectoriesDimitri de Jonghe, Georges G. E. Gielen. 91-94 [doi]
- Optimal statistical chip dispositionVladimir Zolotov, Jinjun Xiong. 95-102 [doi]
- Temperature aware statistical static timing analysisArtem Rogachev, Lu Wan, Deming Chen. 103-110 [doi]
- Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffersBing Li, Ning Chen. 111-117 [doi]
- Improving shared cache behavior of multithreaded object-oriented applications in multicoresMahmut T. Kandemir, Shekhar Srikantaiah, Seung Woo Son. 118-125 [doi]
- CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation techniqueMohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran. 126-133 [doi]
- Cooperative parallelizationPraveen Yedlapalli, Emre Kultursay, Mahmut T. Kandemir. 134-141 [doi]
- Optimizing data locality using array tilingWei Ding, Yuanrui Zhang, Jun Liu, Mahmut T. Kandemir. 142-149 [doi]
- Assuring application-level correctness against soft errorsJason Cong, Karthik Gururaj. 150-157 [doi]
- The role of EDA in digital print automation and infrastructure optimizationKrishnendu Chakrabarty, Gary Dispoto, Rick Bellamy, Jun Zeng. 158-161 [doi]
- Toward efficient spatial variation decomposition via sparse regressionWangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar. 162-169 [doi]
- REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variationsCharles Lamech, Jim Aarestad, Jim Plusquellic, Reza M. Rad, Kanak Agarwal. 170-177 [doi]
- Accelerating aerial image simulation with GPUHongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel. 178-184 [doi]
- Combined loop transformation and hierarchy allocation for data reuse optimizationJason Cong, Peng Zhang, Yi Zou. 185-192 [doi]
- High-level synthesis with distributed controller for fast timing closureSeokhyun Lee, Kiyoung Choi. 193-199 [doi]
- Synthesis of parallel binary machinesElena Dubrova. 200-206 [doi]
- Chemical-mechanical polishing aware application-specific 3D NoC designWooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan. 207-212 [doi]
- Application-aware deadlock-free oblivious routing based on extended turn-modelAli Shafiee, Mahdy Zolghadr, Mohammad Arjomand, Hamid Sarbazi-Azad. 213-218 [doi]
- Co-design of channel buffers and crossbar organizations in NoCs architecturesAvinash Karanth Kodi, Randy Morris, Dominic DiTomaso, Ashwini Sarathy, Ahmed Louri. 219-226 [doi]
- Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updatedHai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra. 227-230 [doi]
- Alternative design methodologies for the next generation logic switchDavide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici. 231-234 [doi]
- Progress and outlook for STT-MRAMYiming Huai, Yuchen Zhou, Ioan Tudosa, Roger Malmhall, Rajiv Ranjan, Jing Zhang. 235 [doi]
- Universal statistical cure for predicting memory lossRajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Helen Li. 236-239 [doi]
- Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuitsGuillaume Prenat, Bernard Dieny, Jean-Pierre Nozieres, Gregory di Pendina, Kholdoun Torki. 240-245 [doi]
- Progress in CMOS-memristor integrationGilberto Medeiros-Ribeiro, Janice H. Nickel, J. Joshua Yang. 246-249 [doi]
- MGR: Multi-level global routerYue Xu, Chris Chu. 250-255 [doi]
- Congestion analysis for global routing via integer programmingHamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth. 256-262 [doi]
- High-quality global routing for multiple dynamic supply voltage designsWen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao. 263-269 [doi]
- The future of clock network synthesisCliff C. N. Sze. 270 [doi]
- Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from VenusJoseph N. Kozhaya, Phillip Restle, Haifeng Qian. 271-275 [doi]
- Clocking design automation in Intel's Core i7 and future designsAli M. El-Husseini, Matthew Morrise. 276-278 [doi]
- Algorithmic tuning of clock trees and derived non-tree structuresIgor L. Markov, DongJin Lee. 279-282 [doi]
- Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancingYen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li. 283-289 [doi]
- A jumper insertion algorithm under antenna ratio and timing constraintsXin Gao, Luca Macchiarulo. 290-297 [doi]
- Exploring high throughput computing paradigm for global routingYiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy. 298-305 [doi]
- Escape routing for staggered-pin-array PCBsYuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang. 306-309 [doi]
- Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planningMatthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa. 310-317 [doi]
- The STeTSiMS STT-RAM simulation and modeling systemClinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan. 318-325 [doi]
- Massively parallel programming models used as hardware description languages: The OpenCL caseMuhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis. 326-333 [doi]
- Neuromorphic modeling abstractions and simulation of large-scale cortical networksJeffrey L. Krichmar, Nikil Dutt, Jayram Moorkanikara Nageswaran, Micah Richert. 334-338 [doi]
- A heterogeneous accelerator platform for multi-subject voxel-based brain network analysisYu Wang 0002, Mo Xu, Ling Ren, Xiaorui Zhang, Di Wu, Yong He, Ningyi Xu, Huazhong Yang. 339-344 [doi]
- Fast statistical model of TiO2 thin-film memristor and design implicationMiao Hu, Hai Li, Robinson E. Pino. 345-352 [doi]
- Accelerated statistical simulation via on-demand Hermite spline interpolationsRouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif. 353-360 [doi]
- Structure preserving reduced-order modeling of linear periodic time-varying systemsTing Mei, Heidi Thornquist, Eric R. Keiter, Scott A. Hutchinson. 361-366 [doi]
- ModSpec: An open, flexible specification framework for multi-domain device modellingDavid Amsallem, Jaijeet S. Roychowdhury. 367-374 [doi]
- Delay optimization using SOP balancingAlan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets. 375-382 [doi]
- Match and replace - A functional ECO engine for multi-error circuit rectificationShao-Lun Huang, Wei-Hsun Lin, Chung-Yang (Ric) Huang. 383-388 [doi]
- Towards completely automatic decoder synthesisHsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang. 389-395 [doi]
- On rewiring and simplification for canonicity in threshold logic circuitsPin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang. 396-403 [doi]
- Inferring assertion for complementary synthesisShengYu Shen, Ying Qin, Jianmin Zhang. 404-411 [doi]
- Statistical aging analysis with process variation considerationSangwoo Han, Joohee Choung, Byung-Su Kim, Bong Hyun Lee, Hungbok Choi, Juho Kim. 412-419 [doi]
- A new method for multiparameter robust stability distribution analysis of linear analog circuitsChanghao Yan, Sheng-Guo Wang, Xuan Zeng. 420-427 [doi]
- Failure diagnosis of asymmetric aging under NBTIJyothi Bhaskarr Velamala, Venkatesa Ravi, Yu Cao. 428-433 [doi]
- In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradationZahra Lak, Nicola Nicolici. 434-441 [doi]
- Online clock skew tuning for timing speculationRong Ye, Feng Yuan, Qiang Xu. 442-447 [doi]
- Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochipsTsung-Wei Huang, Tsung-Yi Ho, Krishnendu Chakrabarty. 448-455 [doi]
- Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneouslyYehua Su, Wenjing Rao. 456-462 [doi]
- Device-architecture co-optimization of STT-RAM based memory for low power embedded systemsCong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak, Yuan Xie. 463-470 [doi]
- STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design viewYaojun Zhang, XiaoBin Wang, Yiran Chen. 471-477 [doi]
- 2011 TAU power grid simulation contest: Benchmark suite and resultsZhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif. 478-481 [doi]
- PowerRush: A linear simulator for power gridJianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. 482-487 [doi]
- Fast static analysis of power grids: Algorithms and implementationsZhiyu Zeng, Tong Xu, Zhuo Feng, Peng Li. 488-493 [doi]
- On the preconditioner of conjugate gradient method - A power grid simulation perspectiveChung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang. 494-497 [doi]
- PTrace: Derivative-free local tracing of bicriterial design tradeoffsAmith Singhee. 498-502 [doi]
- A methodology for local resonant clock synthesis using LC-assisted local clock buffersWalter James Condley, Xuchu Hu, Matthew R. Guthaus. 503-506 [doi]
- ∗-tree representation and its applications to analog placementHui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu. 507-511 [doi]
- ∗-trees for analog placement with symmetry and regularity considerationsPang-Yen Chou, Hung-Chih Ou, Yao-Wen Chang. 512-516 [doi]
- Fast analog layout prototyping for nanometer design migrationYi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen. 517-522 [doi]
- Model order reduction of fully parameterized systems by recursive least square optimizationZheng Zhang, Ibrahim M. Elfadel, Luca Daniel. 523-530 [doi]
- Fast poisson solver preconditioned method for robust power grid analysisJianlei Yang, Yici Cai, Qiang Zhou, Jin Shi. 531-536 [doi]
- Modeling and estimation of power supply noise using linear programmingFarshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori. 537-542 [doi]
- Power grid analysis with hierarchical support graphsXueqian Zhao, Jia Wang, Zhuo Feng, Shiyan Hu. 543-547 [doi]
- Vectorless verification of RLC power grids with transient current constraintsXuanxing Xiong, Jia Wang. 548-554 [doi]
- Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICsMohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim. 555-562 [doi]
- Full-chip through-silicon-via interfacial crack analysis and optimization for 3D ICMoongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim. 563-570 [doi]
- Variation-aware electromigration analysis of power/ground networksDi-an Li, Malgorzata Marek-Sadowska. 571-576 [doi]
- Low-power multiple-bit upset tolerant memory optimizationSeokjoong Kim, Matthew R. Guthaus. 577-581 [doi]
- Mitigating FPGA interconnect soft errors by in-place LUT inversionNaifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He. 582-586 [doi]
- Debugging with dominance: On-the-fly RTL debug solution implicationsHratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour. 587-594 [doi]
- Simulation-based signal selection for state restoration in silicon debugDebapriya Chatterjee, Calvin McCarter, Valeria Bertacco. 595-601 [doi]
- Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniquesBo-Han Wu, Chun-Ju Yang, Chia-Cheng Tso, Chung-Yang (Ric) Huang. 602-607 [doi]
- Identifying the optimal energy-efficient operating points of parallel workloadsRyan Cochran, Can Hankendi, Ayse Kivilcim Coskun, Sherief Reda. 608-615 [doi]
- System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimediaHaris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran. 616-623 [doi]
- Balanced reconfiguration of storage banks in a hybrid electrical energy storage systemYounghyun Kim, Sangyoung Park, Yanzhi Wang, Qing Xie, Naehyuck Chang, Massimo Poncino, Massoud Pedram. 624-631 [doi]
- Multilevel tree fusion for robust clock networksDongJin Lee, Igor L. Markov. 632-639 [doi]
- Implementation of pulsed-latch and pulsed-register circuits to minimize clocking powerSeungwhun Paik, Gi-Joon Nam, Youngsoo Shin. 640-646 [doi]
- Useful-skew clock optimization for multi-power mode designsHsuan-Ming Chou, Hao Yu, Shih-Chieh Chang. 647-650 [doi]
- ATree-based topology synthesis for on-chip networkJason Cong, Yuhui Huang, Bo Yuan. 651-658 [doi]
- Formal verification of phase-locked loops using reachability analysis and continuizationMatthias Althoff, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, Larry T. Pileggi. 659-666 [doi]
- MACACO: Modeling and analysis of circuits for approximate computingRangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan. 667-673 [doi]
- Property-specific sequential invariant extraction for SAT-based unbounded model checkingHu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang. 674-678 [doi]
- Automatic formal verification of multithreaded pipelined microprocessorsMiroslav N. Velev, Ping Gao 0002. 679-686 [doi]
- Accelerating RTL simulation with GPUsHao Qian, Yangdong Deng. 687-693 [doi]
- CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniquesSheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi. 694-701 [doi]
- A trace compression algorithm targeting power estimation of long benchmarksAndrey Ayupov, Steven M. Burns. 702-707 [doi]
- A theoretical probabilistic simulation framework for dynamic power estimationLei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz. 708-715 [doi]
- Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal managementHai Wang, Sheldon X.-D. Tan, Guangdeng Liao, Rafael Quintanilla, Ashish Gupta 0007. 716-723 [doi]
- Gate sizing and device technology selection algorithms for high-performance industrial designsMuhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu. 724-731 [doi]
- Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimizationJunjun Gu, Gang Qu, Lin Yuan, Cheng Zhuo. 732-735 [doi]
- The approximation scheme for peak power driven voltage partitioningJia Wang, Xiaodao Chen, Chen Liao, Shiyan Hu. 736-741 [doi]
- Timing ECO optimization via Bézier curve smoothing and fixability identificationHua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang. 742-746 [doi]
- Test-data volume and scan-power reduction with low ATE interface for multi-core SoCsVasileios Tenentes, Xrysovalantis Kavousianos. 747-754 [doi]
- Post-silicon bug diagnosis with inconsistent executionsAndrew DeOrio, Daya Shanker Khudia, Valeria Bertacco. 755-761 [doi]
- On proving the efficiency of alternative RF testsNathan Kupp, Haralampos-G. D. Stratigopoulos, Petros Drineas, Yiorgos Makris. 762-767 [doi]
- Statistical defect-detection analysis of test sets using readily-available tester dataXiaochun Yu, R. D. (Shawn) Blanton. 768-773 [doi]
- A robust architecture for post-silicon skew tuningMac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang. 774-778 [doi]
- A low-swing crossbar and link generator for low-power networks-on-chipChia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Li-Shiuan Peh. 779-786 [doi]
- Exploring heterogeneous NoC design spaceHui Zhao, Mahmut T. Kandemir, Wei Ding, Mary Jane Irwin. 787-793 [doi]
- Synchronous elasticization at a reduced cost: Utilizing the ultra simple fork and controller mergingEliyah Kilada, Kenneth S. Stevens. 794-801 [doi]
- Robust passive hardware meteringSheng Wei, Ani Nahapetian, Miodrag Potkonjak. 802-809 [doi]
- A framework for accelerating neuromorphic-vision algorithms on FPGAsMichael DeBole, Ahmed Al-Maashri, Matthew Cotter, Chi-Li Yu, Chaitali Chakrabarti, Vijaykrishnan Narayanan. 810-813 [doi]