Jacob T. Grycel, Robert J. Walls. DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs. In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020. pages 1-5, IEEE, 2020. [doi]
Abstract is missing.