A 6- μ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Jianping Guo, Ka Nang Leung. A 6- μ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology. J. Solid-State Circuits, 45(9):1896-1905, 2010. [doi]

Abstract

Abstract is missing.