A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead

Zheng Guo, Jami Wiedemer, Yusung Kim, Prithvee Sundararajan Ramamoorthy, Prateeksha Bindiganavile Sathyaprasad, Smita Shridharan, Daeyeon Kim, Eric Karl. A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead. In IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020. pages 1-2, IEEE, 2020. [doi]

Abstract

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