An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Zhenhua Guo, Yanxia Wu, Guoyin Zhang, Tianxiang Sui. An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler. In Chenggang Wu, Albert Cohen, editors, Advanced Parallel Processing Technologies - 10th International Symposium, APPT 2013, Stockholm, Sweden, August 27-28, 2013, Revised Selected Papers. Volume 8299 of Lecture Notes in Computer Science, pages 307-318, Springer, 2013. [doi]

This author has not been identified. Look up 'Zhenhua Guo' in GoogleThis author has not been identified. Look up 'Yanxia Wu' in GoogleThis author has not been identified. Look up 'Guoyin Zhang' in GoogleThis author has not been identified. Look up 'Tianxiang Sui' in Google

runs on WebDSL