Zhenhua Guo, Yanxia Wu, Guoyin Zhang, Tianxiang Sui. An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler. In Chenggang Wu, Albert Cohen, editors, Advanced Parallel Processing Technologies - 10th International Symposium, APPT 2013, Stockholm, Sweden, August 27-28, 2013, Revised Selected Papers. Volume 8299 of Lecture Notes in Computer Science, pages 307-318, Springer, 2013. [doi]
@inproceedings{GuoWZS13, title = {An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler}, author = {Zhenhua Guo and Yanxia Wu and Guoyin Zhang and Tianxiang Sui}, year = {2013}, doi = {10.1007/978-3-642-45293-2_23}, url = {http://dx.doi.org/10.1007/978-3-642-45293-2_23}, researchr = {https://researchr.org/publication/GuoWZS13}, cites = {0}, citedby = {0}, pages = {307-318}, booktitle = {Advanced Parallel Processing Technologies - 10th International Symposium, APPT 2013, Stockholm, Sweden, August 27-28, 2013, Revised Selected Papers}, editor = {Chenggang Wu and Albert Cohen}, volume = {8299}, series = {Lecture Notes in Computer Science}, publisher = {Springer}, isbn = {978-3-642-45292-5}, }