Avaneendra Gupta, John P. Hayes. Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. In 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India. pages 453-459, IEEE Computer Society, 1999. [doi]
No references recorded for this publication.
No citations of this publication recorded.