Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process - researchr publication

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Hyunju Ham, Toshimasa Matsuoka, Jun Wang 0009, Kenji Taniguchi 0001. Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process. IEICE Electronic Express, 8(6):353-359, 2011. [doi]

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