Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture - researchr publication

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Fazal Hameed, Lars Bauer, Jörg Henkel. Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. In The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014. pages 1-6, ACM, 2014. [doi]

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