Table of Contents

• Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel FingerprintingYu Liu, Ke Huang, Yiorgos Makris. 1-6 [doi]
• Computing with Hybrid CMOS/STO CircuitsMehdi Kabir, Mircea R. Stan. 1-6 [doi]
• Deterministic Crash Recovery for NAND Flash Based Storage SystemsChi Zhang, Yi Wang, Tianzheng Wang, Renhai Chen, Duo Liu, Zili Shao. 1-6 [doi]
• Parallel FPGA Routing based on the Operator FormulationYehdhih Ould Mohammed Moctar, Philip Brisk. 1-6 [doi]
• On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die StackingDuckhwan Kim, Saibal Mukhopadhyay. 1-6 [doi]
• A Time-Unrolling Method to Compute Sensitivity of Dynamic SystemsFrank Liu, Peter Feldmann. 1-6 [doi]
• Verification of Non-Mainline Functions in Todays Processor ChipsJohannes Koesters, Alex Goryachev. 1-3 [doi]
• Beyond ECDSA and RSA: Lattice-based Digital Signatures on Constrained DevicesTobias Oder, Thomas Pöppelmann, Tim Güneysu. 1-6 [doi]
• A New Field-assisted Access Scheme of STT-RAM with Self-reference CapabilityEnes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen. 1-6 [doi]
• Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research ChallengesJen-Hendrik Oetjens, Nico Bannow, M. Becker, Oliver Bringmann, Andreas Burger, M. Chaari, S. Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, H. M. Le, Mauderer Mauderer, Wolfgang Müller 0002, D. Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, B.-A. Tabacaru, Alexander Viehl. 1-6 [doi]
• TI-TRNG: Technology Independent True Random Number GeneratorMd. Tauhidur Rahman, Kan Xiao, Domenic Forte, Xuhei Zhang, Jerry Shi, Mohammad Tehranipoor. 1-6 [doi]
• Symbolic Analysis of Dataflow Applications Mapped onto Shared Heterogeneous ResourcesFirew Siyoum, Marc Geilen, Henk Corporaal. 1-6 [doi]
• FIGHT-Metric: Functional Identification of Gate-Level Hardware TrustworthinessDean Sullivan, Jeff Biggers, Guidong Zhu, Shaojie Zhang, Yier Jin. 1-4 [doi]
• A SystemC Virtual Prototyping based Methodology for Multi-Standard SoC Functional VerificationZhimiao Chen, Yifan Wang, Lei Liao, Ye Zhang, Aytac Atac, Jan Henning Müller, Ralf Wunderlich, Stefan Heinen. 1-6 [doi]
• The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability PerspectivesMuhammad Shafique, Siddharth Garg, Jörg Henkel, Diana Marculescu. 1-6 [doi]
• Space-Efficient Multiversion Index Scheme for PCM-based Embedded Database SystemsYuan-Hung Kuan, Yuan-Hao Chang, Po-Chun Huang, Kam-yiu Lam. 1-6 [doi]
• Computation Offloading by Using Timing Unreliable Components in Real-Time SystemsWei Liu, Jian-Jia Chen, Anas Toma, Tei-Wei Kuo, Qingxu Deng. 1-6 [doi]
• Design and Implementation of a Dynamic Component Model for Federated AUTOSAR SystemsZe Ni, Avenir Kobetski, Jakob Axelsson. 1-6 [doi]
• Metasynthesis for Designing Automotive SoCsWolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal. 1-6 [doi]
• Coverage Learned Targeted Validation for Incremental HW ChangesMonica Farkash, Bryan G. Hickerson, Michael Behm. 1-6 [doi]
• Multi-Layer Dependability: From Microarchitecture to Application LevelJörg Henkel, Lars Bauer, Hongyan Zhang, Semeen Rehman, Muhammad Shafique. 1-6 [doi]
• On Trading Wear-leveling with Heal-levelingYu-Ming Chang, Yuan-Hao Chang, Jian-Jia Chen, Tei-Wei Kuo, Hsiang-Pang Li, Hang-Ting Lue. 1-6 [doi]
• Techniques for Foundry IdentificationJames Bradley Wendt, Farinaz Koushanfar, Miodrag Potkonjak. 1-6 [doi]
• Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure CodesParthasarathy M. B. Rao, Mojtaba Ebrahimi, Razi Seyyedi, Mehdi Baradaran Tahoori. 1-6 [doi]
• Reduction Operator for Wide-SIMDs ReconsideredLuc Waeijen, Dongrui She, Henk Corporaal, Yifan He. 1-6 [doi]
• An Efficient Bi-criteria Flow Channel Routing Algorithm For Flow-based Microfluidic BiochipsChun-Xun Lin, Chih-Hung Liu, I.-Che Chen, D. T. Lee, Tsung-Yi Ho. 1-6 [doi]
• BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon ValidationKetul Sutaria, Athul Ramkumar, Rongjun Zhu, Renju Rajveev, Yao Ma, Yu Cao. 1-6 [doi]
• Retention Trimming for Wear Reduction of Flash Memory Storage SystemsLiang Shi, Kaijie Wu, Mengying Zhao, Chun Jason Xue, Edwin Hsing-Mean Sha. 1-6 [doi]
• Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuitsParijat Mukherjee, Peng Li. 1-6 [doi]
• Contactless Stacked-die Testing for Pre-bond InterposersJui-Hung Chien, Ruei-Siang Hsu, Hsueh-Ju Lin, Ka-Yi Yeh, Shih-Chieh Chang. 1-6 [doi]
• ePlace: Electrostatics Based Placement Using Nesterov's MethodJingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis J.-. H. Huang, Chin-Chi Teng, Chung-Kuan Cheng. 1-6 [doi]
• Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded MemoryAnirudh Iyengar, Swaroop Ghosh. 1-6 [doi]
• Circuit Camouflage Integration for Hardware IP ProtectionRonald P. Cocchi, James P. Baukus, Lap Wai Chow, Bryan J. Wang. 1-5 [doi]
• Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous PlatformsYoungsub Ko, Taeyoung Kim, Youngmin Yi, Myungsun Kim, Soonhoi Ha. 1-6 [doi]
• Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible SolutionsSelçuk Köse. 1-6 [doi]
• Flushing-Enabled Loop Pipelining for High-Level SynthesisSteve Dai, Mingxing Tan, Kecheng Hao, Zhiru Zhang. 1-6 [doi]
• Selective Inversion of Inductance Matrix for Large-Scale Sparse RLC SimulationIfigeneia Apostolopoulou, Konstantis Daloukas, Nestor E. Evmorfopoulos, George I. Stamoulis. 1-6 [doi]
• Ultra Low-Power implementation of ECC on the ARM Cortex-M0+Ruan de Clercq, Leif Uhsadel, Anthony Van Herrewege, Ingrid Verbauwhede. 1-6 [doi]
• Multi-Objective Local-Search Optimization using Reliability Importance MeasuringFaramarz Khosravi, Felix Reimann, Michael Glaß, Jürgen Teich. 1-6 [doi]
• A Rigorous Graphical Technique for Predicting Sub-harmonic Injection Locking in LC OscillatorsPalak Bhushan. 1-8 [doi]
• NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon EraJia Zhan, Yuan Xie, Guangyu Sun. 1-6 [doi]
• An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC ProcessorDevendra Rai, Pengcheng Huang, Nikolay Stoimenov, Lothar Thiele. 1-6 [doi]
• An Efficient Wire Routing and Wire Sizing Algorithm for Weight Minimization of Automotive SystemsChung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli. 1-6 [doi]
• PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFsJoonho Kong, Farinaz Koushanfar, Praveen K. Pendyala, Ahmad-Reza Sadeghi, Christian Wachsmann. 1-6 [doi]
• Walking Pads: Managing C4 Placement for Transient Voltage Noise MinimizationKe Wang, Brett H. Meyer, Runjie Zhang, Micrea Stan, Kevin Skadron. 1-6 [doi]
• Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DACMark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin. 1-6 [doi]
• Monitoring Reliability in Embedded Processors - A Multi-layer ViewVikas Chandra. 1-6 [doi]
• High-Level Synthesis for Run-Time Hardware Trojan Detection and RecoveryXiaotong Cui, Kun Ma, Liang Shi, Kaijie Wu. 1-6 [doi]
• Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic OptimizationLuca Gaetano Amarú, Pierre-Emmanuel Gaillardon, Giovanni De Micheli. 1-6 [doi]
• POLAR 2.0: An Effective Routability-Driven PlacerTao Lin, Chris Chu. 1-6 [doi]
• Dynamic Power Management of Off-Chip Links for Hybrid Memory CubesJunwhan Ahn, Sungjoo Yoo, Kiyoung Choi. 1-6 [doi]
• Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New MeasurementsLi Yu, Sharad Saxena, Christopher Hess, Abe Elfadel, Dimitri A. Antoniadis, Duane S. Boning. 1-6 [doi]
• MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache AnalysisJosef Schneider, Jorgen Peddersen, Sri Parameswaran. 1-6 [doi]
• Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design CaseWulong Liu, Guoqing Chen, Xue Han, Yu Wang, Yuan Xie, Huazhong Yang. 1-6 [doi]
• Ultra-Low Power Design of Wearable Cardiac Monitoring SystemsRuben Braojos, Hossein Mamaghanian, Alair Dias Junior, Giovanni Ansaloni, David Atienza, Francisco J. Rincón, Srinivasan Murali. 1-6 [doi]
• Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore SystemsAnup Das 0001, Rishad A. Shafik, Geoff V. Merrett, Bashir M. Al-Hashimi, Akash Kumar, Bharadwaj Veeravalli. 1-6 [doi]
• BEOL Scaling Limits and Next Generation Technology ProspectsAzad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja. 1-6 [doi]
• Probabilistic Bug Localization via Statistical Inference based on Partially Observed DataSangho Youn, Chenjie Gu, Jaeha Kim. 1-6 [doi]
• A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher AlgorithmsWeiwei Shan, Longxing Shi, Xingyuan Fu, Xiao Zhang, Chaoxuan Tian, Zhipeng Xu, Jun Yang, Jie Li. 1-6 [doi]
• Ontology-guided Conceptual Analysis of Design SpecificationsArunprasath Shankar, Bhanu Pratap Singh, Francis G. Wolff, Christos A. Papachristou. 1-6 [doi]
• One-Shot Calibration of RF Circuits Based on Non-Intrusive SensorsMartin Andraud, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu. 1-2 [doi]
• SLC-enabled Wear Leveling for MLC PCM Considering Process VariationMengying Zhao, Lei Jiang, Youtao Zhang, Chun Jason Xue. 1-6 [doi]
• Detecting Reliability Attacks during Split Fabrication using Test-only BEOL StackKaushik Vaidyanathan, Bishnu P. Das, Larry Pileggi. 1-6 [doi]
• Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold DesignsYu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wan-yu Wen, Yiyu Shi, Shih-Chieh Chang. 1-6 [doi]
• Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner BasesTim Pruss, Priyank Kalla, Florian Enescu. 1-6 [doi]
• Designing Stealthy Trojans with Sequential Logic: A Stream Cipher Case StudyMukesh Reddy Rudra, Nimmy Anna Daniel, Varun Nagoorkar, David H. K. Hoe. 1-4 [doi]
• A New Asynchronous Pipeline Template for Power and Performance OptimizationKuan-Hsien Ho, Yao-Wen Chang. 1-6 [doi]
• Functional ECO Using Metal-Configurable Gate-Array Spare CellsHua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang. 1-6 [doi]
• Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut ProcessIou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang. 1-6 [doi]
• EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDsRen-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li. 1-6 [doi]
• Accelerator-Rich Architectures: Opportunities and ProgressesJason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Karthik Gururaj, Glenn Reinman. 1-6 [doi]
• Sufficient Temporal Independence and Improved Interrupt Latencies in a Real-Time HypervisorMatthias Beckert, Moritz Neukirchner, Rolf Ernst, Stefan M. Petters. 1-6 [doi]
• A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded SoftwareGiovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale. 1-6 [doi]
• A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring OptimizationsZehan Cui, Licheng Chen, Yungang Bao, Mingyu Chen. 1-6 [doi]
• ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon EraFlorian Kriebel, Semeen Rehman, Duo Sun, Muhammad Shafique, Jörg Henkel. 1-6 [doi]
• Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUsXiaoming Chen, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang. 1-6 [doi]
• Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial OptimizationYe Wang, Michael Orshansky, Constantine Caramanis. 1-6 [doi]
• An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse BuffersJason Cong, Peng Li, Bingjun Xiao, Peng Zhang. 1-6 [doi]
• Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offsKan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides. 1-6 [doi]
• Demystifying Energy Usage in SmartphonesXiang Chen, Yiran Chen, Mian Dong, Jianzhong (Charlie) Zhang. 1-5 [doi]
• Balancing Scalability and Uniformity in SAT Witness GeneratorSupratik Chakraborty, Kuldeep S. Meel, Moshe Y. Vardi. 1-6 [doi]
• Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack MemoryMengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Helen Li. 1-6 [doi]
• Design Methods for Augmented Reality In-Vehicle Infotainment SystemsQing Rao, Christian Grünler, Markus Hammori, Samarjit Chakraborty. 1-6 [doi]
• C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case DesignsChen-Hsuan Lin, Lu Wan, Deming Chen. 1-6 [doi]
• Power-Aware NoCs through Routing and Topology ReconfigurationRitesh Parikh, Reetuparna Das, Valeria Bertacco. 1-6 [doi]
• REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region CoverageWei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He. 1-6 [doi]
• A Cost Efficient Online Algorithm for Automotive Idling ReductionChuansheng Dong, Haibo Zeng, Minghua Chen. 1-6 [doi]
• Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire CouplingYarui Peng, Dusan Petranovic, Sung Kyu Lim. 1-6 [doi]
• MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse CorrectionJhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan. 1-6 [doi]
• Data Mining In EDA - Basic Principles, Promises, and ConstraintsLi-C. Wang, Magdy S. Abadir. 1-6 [doi]
• Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic BiochipsQin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai. 1-6 [doi]
• Early-Stage Power Grid Design: Extraction, Modeling and OptimizationCheng Zhuo, Houle Gan, Wei-Kai Shih. 1-6 [doi]
• Density-aware Detailed Placement with Instant LegalizationSergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang. 1-6 [doi]
• Post-Routing Latch Optimization for Timing ClosureStephan Held, Ulrike Schorr. 1-6 [doi]
• Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store EliminationHsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang, Ting-Chin Yang, Li-Yue Huang, Ching-Hao Chuang, Meng-Fan Chang, Tien-Fu Chen. 1-6 [doi]
• Directed Self-Assembly (DSA) Template Pattern VerificationZigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang. 1-6 [doi]
• ClusRed: Clustering and Network Reduction Based Probabilistic Optimal Power Flow Analysis for Large-Scale Smart GridsYi Liang, Deming Chen. 1-6 [doi]
• Neuro Inspired Computing with Coupled Relaxation OscillatorsSuman Datta, Nikhil Shukla, Matthew Cotter, Abhinav Parihar, Arijit Raychowdhury. 1-6 [doi]
• Automatic Verification of Floating Point UnitsUdo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky. 1-6 [doi]
• Area-Efficient Event Stream Ordering for Runtime Observability of Embedded SystemsJong Chul Lee, Roman Lysecky. 1-6 [doi]
• Approximate property checking of mixed-signal circuitsParijat Mukherjee, Chirayu S. Amin, Peng Li. 1-6 [doi]
• A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCsGiuseppe Di Guglielmo, Christian Pilato, Luca P. Carloni. 1-6 [doi]
• Code Coverage of Assertions Using RTL Source Code AnalysisViraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan. 1-6 [doi]
• System-Level Security for Network Processors with Hardware MonitorsKekai Hu, Tilman Wolf, Thiago Teixeira, Russell Tessier. 1-6 [doi]
• LiVe: Timely Error Detection in Light-Lockstep Safety Critical SystemsCarles Hernández, Jaume Abella. 1-6 [doi]
• Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCMKeni Qiu, Qing'an Li, Chun Jason Xue. 1-6 [doi]
• VIX: Virtual Input Crossbar for Efficient Switch AllocationSupriya Rao, Supreet Jeloka, Reetuparna Das, David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge. 1-6 [doi]
• Variation Aware Cache Partitioning for Multithreaded ProgramsVivek J. Kozhikkottu, Abhisek S. Pan, Vijay S. Pai, Sujit Dey, Anand Raghunathan. 1-6 [doi]
• Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICsWen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang. 1-6 [doi]
• Throughput Optimization for SADP and E-beam based Manufacturing of 1D LayoutYixiao Ding, Chris Chu, Wai-Kei Mak. 1-6 [doi]
• Typical Worst Case Response-Time Analysis and its Use in Automotive Network DesignSophie Quinton, Torsten T. Bone, Julien Hennig, Moritz Neukirchner, Mircea Negrean, Rolf Ernst. 1-6 [doi]
• Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST CurvesDebapriya Basu Roy, Debdeep Mukhopadhyay, Masami Izumi, Junko Takahashi. 1-6 [doi]
• Fort-NoCs: Mitigating the Threat of a Compromised NoCDean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy. 1-6 [doi]
• A Secure but still Safe and Low Cost Automotive Communication TechniqueRafael Zalman, Albrecht Mayer. 1-5 [doi]
• Translation Validation for Stateflow to CPrahladavaradan Sampath, A. C. Rajeev, S. Ramesh. 1-6 [doi]
• Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant CachesMark Gottscho, Abbas BanaiyanMofrad, Nikil Dutt, Alex Nicolau, Puneet Gupta. 1-6 [doi]
• Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic BiochipsSudip Roy, Srijan Kumar, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya, Krishnendu Chakrabarty. 1-6 [doi]
• Thermal-Sustainable Power Budgeting for Dynamic ThreadingXing Hu, Yi Xu, Jun Ma, Guoqing Chen, Yu Hu, Yuan Xie. 1-6 [doi]
• darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark SiliconHaseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran. 1-6 [doi]
• Catch Your Attention: Quality-retaining Power Saving on Mobile OLED DisplaysChun-Han Lin, Chih-Kai Kang, Pi-Cheng Hsiu. 1-6 [doi]
• Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle EffectsRyan H.-M. Huang, Charles H.-P. Wen. 1-6 [doi]
• Physics-based Electromigration Assessment for Power Grid NetworksXin Huang, Tan Yu, Valeriy Sukharev, Sheldon X.-D. Tan. 1-6 [doi]
• An Efficient Two-level DC Operating Points Finder for Transistor CircuitsJian Deng, Kim Batselier, Yang Zhang, Ngai Wong. 1-6 [doi]
• Content-centric Display Energy Management for Mobile DevicesDongwon Kim, Nohyun Jung, Hojung Cha. 1-6 [doi]
• CGPA: Coarse-Grained Pipelined AcceleratorsFeng Liu, Soumyadeep Ghosh, Nick P. Johnson, David I. August. 1-6 [doi]
• dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced EffectsSemeen Rehman, Florian Kriebel, Duo Sun, Muhammad Shafique, Jörg Henkel. 1-6 [doi]
• Scalable Certification Framework for Behavioral Synthesis Front-EndZhenkun Yang, Kecheng Hao, Kai Cong, Li Lei, Sandip Ray, Fei Xie. 1-6 [doi]
• On Timing Closure: Buffer Insertion for Hold-Violation RemovalPei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe. 1-6 [doi]
• Quantitative Analysis of Control Flow Checking Mechanisms for Soft ErrorsAviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, Carole-Jean Wu. 1-6 [doi]
• MATEX: A Distributed Framework for Transient Simulation of Power Distribution NetworksHao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng. 1-6 [doi]
• Hardware-Assisted Fine-Grained Control-Flow Integrity: Towards Efficient Protection of Embedded Systems Against Software ExploitationLucas Davi, Patrick Koeberl, Ahmad-Reza Sadeghi. 1-6 [doi]
• Post-Silicon Validation of the IBM POWER8 ProcessorAmir Nahir, Manoj Dusanapudi, Shakti Kapoor, Kevin Reick, Wolfgang Roesner, Klaus-Dieter Schubert, Keith Sharp, Greg Wetli. 1-6 [doi]
• Row Based Dual-VDD Island Generation and PlacementHua Xiang, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu. 1-6 [doi]
• TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel SynthesisMahmoud Elbayoumi, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Michael S. Hsiao, Mustafa ElNainay. 1-6 [doi]
• Quality-of-Service for a High-Radix SwitchNilmini Abeyratne, Supreet Jeloka, Yiping Kang, David Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge. 1-6 [doi]
• Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level ResilienceVeit Kleeberger, Petra R. Maier, Ulf Schlichtmann. 1-6 [doi]
• Resource Efficient Mobile Communications for Crowd-SensingChristian Wietfeld, Christoph Ide, Bjoern Dusza. 1-6 [doi]
• Exact One-pass Synthesis of Digital Microfluidic BiochipsOliver Keszocze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler. 1-6 [doi]
• Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB NetworksPhilip Axer, Daniel Thiele, Rolf Ernst, Jonas Diemer. 1-6 [doi]
• Branch-Aware Loop Mapping on CGRAsMahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula. 1-6 [doi]
• BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated CircuitsChenlei Fang, Fan Yang, Xuan Zeng, Xin Li. 1-6 [doi]
• GUARD: GUAranteed Reliability in Dynamically Reconfigurable SystemsHongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel. 1-6 [doi]
• Multi-Layer Memory ResiliencyNikil Dutt, Puneet Gupta, Alex Nicolau, Abbas BanaiyanMofrad, Mark Gottscho, Majid Shoushtari. 1-6 [doi]
• Steep Slope Devices: Enabling New Architectural ParadigmsKarthik Swaminathan, Huichu Liu, Xueqing Li, Moon Seok Kim, Jack Sampson, Vijaykrishnan Narayanan. 1-6 [doi]
• Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based ComputingAbbas Rahimi, Amirali Ghofrani, Miguel Angel Lastras-Montano, Kwang-Ting Cheng, Luca Benini, Rajesh K. Gupta. 1-6 [doi]
• Schedule Integration Framework for Time-Triggered Automotive ArchitecturesFlorian Sagstetter, Sidharta Andalam, Peter Waszecki, Martin Lukasiewycz, Hauke Stähle, Samarjit Chakraborty, Alois Knoll. 1-6 [doi]
• An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video ProcessingMichael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini. 1-6 [doi]
• A Highly Flexible Ring Oscillator PUFMingze Gao, Khai Lai, Gang Qu. 1-6 [doi]
• Fault-tolerant Routing for On-chip Network Without Using Virtual ChannelsPengju Ren, Qingxin Meng, Xiaowei Ren, Nanning Zheng. 1-6 [doi]
• Hardware/Software Co-Design of Elliptic-Curve Cryptography for Resource-Constrained ApplicationsAndrea Höller, Norbert Druml, Christian Kreiner, Christian Steger, Tomaz Felicijan. 1-6 [doi]
• FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCsHaris Javaid, Yusuke Yachide, Su Myat Min Shwe, Haseeb Bokhari, Sri Parameswaran. 1-6 [doi]
• Aspect-oriented Modeling of Attacks in Automotive Cyber-Physical SystemsArmin Wasicek, Patricia Derler, Edward A. Lee. 1-6 [doi]
• Enabling Dynamic Heterogeneity Through Core-on-Core StackingVasileios Kontorinis, Mohammad K. Tavana, Mohammad H. Hajkazemi, Dean M. Tullsen, Houman Homayoun. 1-6 [doi]
• On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage VariationsTing Wang, Qiang Xu. 1-6 [doi]
• Using a High-Level Test Generation Expert System for Testing In-Car NetworksAllon Adir, Alex Goryachev, Lev Greenberg, Tamer Salman. 1-6 [doi]
• Automated Specification and Verification of Functional Safety in Heavy-Vehicles: the VeriSpec ApproachGuillermo Rodríguez-Navas, Cristina Cerschi Seceleanu, Hans Hansson, Mattias Nyberg, Oscar Ljungkrantz, Henrik Lönn. 1-4 [doi]
• Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache ArchitectureFazal Hameed, Lars Bauer, Jörg Henkel. 1-6 [doi]
• Advanced Techniques for Designing Stealthy Hardware TrojansNektarios Georgios Tsoutsos, Charalambos Konstantinou, Michail Maniatakos. 1-4 [doi]
• Power-Aware Deployment and Control of Forced-Convection and Thermoelectric CoolersMohammad Javad Dousti, Massoud Pedram. 1-6 [doi]
• Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding AnalysisYuankun Xue, Zhiliang Qian, Paul Bogdan, Fan Ye, Chi-Ying Tsui. 1-6 [doi]
• Advanced Diagnosis: SBST and BIST Integration in Automotive E/E ArchitecturesFelix Reimann, Michael Glaß, Jürgen Teich, Alejandro Cook, Laura Rodríguez Gómez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein. 1-9 [doi]
• Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM ArraysSeyedhamidreza Motaman, Swaroop Ghosh. 1-2 [doi]
• SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core SystemsMohammad Fattah, Maurizio Palesi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 1-6 [doi]
• On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles PerspectiveMoongon Jung, Taigon Song, Yang Wan, Yarui Peng, Sung Kyu Lim. 1-6 [doi]
• DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore SimulationChien-Chih Chen, Yin-Chi Peng, Cheng-Fen Chen, Wei-Shan Wu, Qinghao Min, Pen-Chung Yew, Weihua Zhang, Tien-Fu Chen. 1-6 [doi]
• Exploring the Heterogeneous Design Space for both Performance and ReliabilityRafael Ubal, Dana Schaa, Perhaad Mistry, Xiang Gong, Yash Ukidave, Zhongliang Chen, Gunar Schirner, David R. Kaeli. 1-6 [doi]
• Scalable Co-Simulation of Functional Models With Accurate Event ExchangeAsim Munawar, Shuichi Shimizu. 1-6 [doi]
• Verification of Transactional Memory in POWER8Allon Adir, Dave Goodman, Daniel Hershcovich, Oz Hershkovitz, Bryan G. Hickerson, Karen Holtz, Wisam Kadry, Anatoly Koyfman, John M. Ludden, Charles Meissner, Amir Nahir, Randall R. Pratt, Mike Schiffli, Brett St. Onge, Brian W. Thompto, Elena Tsanko, Avi Ziv. 1-6 [doi]
• Low-cost On-Chip Structures for Combating Die and IC RecyclingUjjwal Guin, Xuehui Zhang, Domenic Forte, Mohammad Tehranipoor. 1-6 [doi]
• Secure Memristor-based Main MemorySachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu. 1-6 [doi]
• Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICsSandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim. 1-6 [doi]
• Routability-Driven Blockage-Aware Macro PlacementYi Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang. 1-6 [doi]
• Reliability-aware Register Binding for Control-Flow Intensive DesignsLiang Chen, Mehdi Baradaran Tahoori. 1-6 [doi]
• A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit IdentificationAdam Waksman, Jeyavijayan Rajendran, Matthew Suozzo, Simha Sethumadhavan. 1-4 [doi]
• Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive CircuitsChi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang. 1-6 [doi]
• On Using Implied Values in EDT-based Test CompressionMarcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. 1-6 [doi]
• Battery Management and Application for Energy-Efficient BuildingsTianshu Wei, Taeyoung Kim, Sangyoung Park, Qi Zhu, Sheldon X.-D. Tan, Naehyuck Chang, Sadrul Ula, Mehdi Maasoumy. 1-6 [doi]
• FPGA Security: From Features to Capabilities to Trusted SystemsSteve Trimberger, Jason Moore. 1-4 [doi]
• OD3P: On-Demand Page Paired PCMMarjan Asadinia, Mohammad Arjomand, Hamid Sarbazi-Azad. 1-6 [doi]
• An Efficient STT-RAM Last Level Cache Architecture for GPUsMohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand, Hamid Sarbazi-Azad. 1-6 [doi]
• Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline CircuitsJiangyi Li, Mingoo Seok. 1-6 [doi]
• Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCsShin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele. 1-6 [doi]
• Low Power GPGPU Computation with Imprecise HardwareHang Zhang, Mateja Putic, John Lach. 1-6 [doi]
• Architecting Dynamic Power Management to be Formally VerifiableDaniel J. Sorin, Opeoluwa Matthews, Meng Zhang. 1-3 [doi]
• Computer-Aided Design of Machine Learning Algorithm: Training Fixed-Point Classifier for On-Chip Low-Power ImplementationHassan Albalawi, Yuanning Li, Xin Li. 1-6 [doi]
• User-Centric Energy-Efficient Scheduling on Multi-Core Mobile DevicesPo-Hsien Tseng, Pi-Cheng Hsiu, Chin-Chiang Pan, Tei-Wei Kuo. 1-6 [doi]
• CACI: Dynamic Current Analysis Towards Robust Recycled Chip IdentificationYu Zheng, Abhishek Basak, Swarup Bhunia. 1-6 [doi]
• Modeling and Experimental Demonstration of Accelerated Self-Healing TechniquesXinfei Guo, Wayne Burleson, Mircea R. Stan. 1-6 [doi]
• An HDL-Based System Design Methodology for Multistandard RF SoC'sAytac Atac, Zhimiao Chen, Lei Liao, Yifan Wang, Martin Schleyer, Ye Zhang, Ralf Wunderlich, Stefan Heinen. 1-6 [doi]
• QMS: Evaluating the Side-Channel Resistance of Masked Software from Source CodeHassan Eldib, Chao Wang, Mostafa M. I. Taha, Patrick Schaumont. 1-6 [doi]
• CAP: Communication Aware ProgrammingJan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker. 1-6 [doi]
• On the Scheduling of Fault-Tolerant Mixed-Criticality SystemsPengcheng Huang, Hoeseok Yang, Lothar Thiele. 1-6 [doi]
• Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware DummificationChi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang. 1-6 [doi]
• Layout Decomposition for Quadruple Patterning Lithography and BeyondBei Yu, David Z. Pan. 1-6 [doi]
• Power management through DVFS and dynamic body biasing in FD-SOI circuitsYeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres. 1-6 [doi]
• Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance VariationsShreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim. 1-6 [doi]
• Parallel Hierarchical Reachability Analysis for Analog VerificationHonghuang Lin, Peng Li. 1-6 [doi]
• Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit ApproachSaman Kiamehr, Thomas H. Osiecki, Mehdi Baradaran Tahoori, Sani Nassif. 1-6 [doi]
• Software Only, Extremely Compact, Keccak-based Secure PRNG on ARM Cortex-MAnthony Van Herrewege, Ingrid Verbauwhede. 1-6 [doi]
• An Automobile Detection Algorithm Development for Automated Emergency Braking SystemLikun Xia, Tran Duc Chung, Khairil Anwar Abu Kassim. 1-6 [doi]
• Statistical Battery Models and Variation-Aware Battery ManagementDonghwa Shin, Enrico Macii, Massimo Poncino. 1-6 [doi]
• Powertrain Co-Simulation using AUTOSAR and the Functional Mockup Interface standardChristoph Stoermer, Ghizlane Tibba. 1 [doi]
• eButton: A Wearable Computer for Health Monitoring and Personal AssistanceMingui Sun, Lora E. Burke, Zhi-Hong Mao, Yiran Chen, Hsin-Chen Chen, Yicheng Bai, Yuecheng Li, Chengliu Li, Wenyan Jia. 1-6 [doi]
• Sense-making from Distributed and Mobile Sensing Data: A Middleware PerspectiveSantanu Sarma, Nalini Venkatasubramanian, Nikil Dutt. 1-6 [doi]
• Integrated CPU-GPU Power Management for 3D Mobile GamesAnuj Pathania, Qing Jiao, Alok Prakash, Tulika Mitra. 1-6 [doi]
• Validation of SoC Firmware-Hardware Flows: Challenges and Solution DirectionsYael Abarbanel, Eli Singerman, Moshe Y. Vardi. 1-4 [doi]
• State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory SystemWujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen. 1-6 [doi]
• Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex HardwareLeonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Glenn Farrall, Franck Wartel, Francisco J. Cazorla. 1-6 [doi]
• System-Level Floorplan-Aware Analysis of Integrated CPU-GPUsVivek S. Nandakumar, Malgorzata Marek-Sadowska. 1-6 [doi]
• Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore SystemsMladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla. 1-6 [doi]
• ApproxIt: An Approximate Computing Framework for Iterative MethodsQian Zhang, Feng Yuan, Rong Ye, Qiang Xu. 1-6 [doi]
• Reverse Engineering and Prevention Techniques for Physical Unclonable Functions Using Side ChannelsSheng Wei, James Bradley Wendt, Ani Nahapetian, Miodrag Potkonjak. 1-6 [doi]
• The First EDA MOOC: Teaching Design Automation to Planet EarthRob A. Rutenbar. 1-6 [doi]