Fazal Hameed, Christian Menard, Jerónimo Castrillón. Efficient STT-RAM last-level-cache architecture to replace DRAM cache. In Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017. pages 141-151, ACM, 2017. [doi]
Abstract is missing.