Table of Contents

• AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memoryJason Cong, Zhenman Fang, Michael Gill, Farnoosh Javadi, Glenn Reinman. 3-14 [doi]
• PHOENIX: efficient computation in memoryMats Rimborg, Pedro Trancoso, Gunnar Carlstedt. 15-25 [doi]
• Near memory key/value lookup accelerationG. Scott Lloyd, Maya Gokhale. 26-33 [doi]
• The sparse data reduction engine: chopping sparse data one byte at a timeJonathan C. Beard. 34-48 [doi]
• Lightweight SIMT core designs for intelligent 3D stacked DRAMChad D. Kersey, Hyesoon Kim, Sudhakar Yalamanchili. 49-59 [doi]
• Identifying the potential of near data processing for apache sparkAhsan Javed Awan, Moriyoshi Ohara, Eduard Ayguadé, Kazuaki Ishizaki, Mats Brorsson, Vladimir Vlassov. 60-67 [doi]
• A bandwidth accurate, flexible and rapid simulating multi-HMC modeling toolPatrick Siegl, Rainer Buchty, Mladen Berekovic. 71-82 [doi]
• CramSim: controller and memory simulatorMichael B. Healy, Seokin Hong. 83-85 [doi]
• Integrating DRAM power-down modes in gem5 and quantifying their impactRadhika Jagtap, Matthias Jung 0001, Wendy Elsasser, Christian Weis, Andreas Hansson, Norbert Wehn. 86-95 [doi]
• Odd-ECC: on-demand DRAM error correcting codesAlirad Malek, Evangelos Vasilakis, Vassilis Papaefstathiou, Pedro Trancoso, Ioannis Sourdis. 96-111 [doi]
• Evaluating hybrid memory cube infrastructure to support high-performance sparse algorithmsKartikay Garg, Jeffrey Young. 112-114 [doi]
• Using run-time reverse-engineering to optimize DRAM refreshDeepak M. Mathew, Éder F. Zulian, Matthias Jung 0001, Kira Kraft, Christian Weis, Bruce Jacob, Norbert Wehn. 115-124 [doi]
• A study of unnecessary write backsChristopher Garman, Xiaochen Guo, Michael Spear. 127-129 [doi]
• SprBlk cache: enabling fault resilience at low voltagesNafiul Alam Siddique, Abdel-Hameed A. Badawy. 130-140 [doi]
• Efficient STT-RAM last-level-cache architecture to replace DRAM cacheFazal Hameed, Christian Menard, Jerónimo Castrillón. 141-151 [doi]
• LMStr: exploring shared hardware controlled scratchpad memory for multicoresNafiul Alam Siddique, Abdel-Hameed A. Badawy, Jeanine Cook, David Resnick. 152-165 [doi]
• Probabilistic replacement strategies for improving the lifetimes of NVM-based cachesElizabeth Reed, Alaa R. Alameldeen, Helia Naeimi, Patrick Stolt. 166-176 [doi]
• Logging in persistent memory: to cache, or not to cache?Mengjie Li, Matheus Ogleari, Jishen Zhao. 177-179 [doi]
• Do superconducting processors really need cryogenic memories?: the case for cold DRAMFrederick A. Ware, Liji Gopalakrishnan, Eric Linstadt, Sally A. McKee, Thomas Vogelsang, Kenneth L. Wright, Craig Hampel, Gary Bronner. 183-188 [doi]
• Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility studySwamit S. Tannu, Douglas M. Carmean, Moinuddin K. Qureshi. 189-195 [doi]
• Memory reliability for cells with strong bit-coupling interferenceKfir Mizrachi, Ilan Bloom, Yuval Cassuto. 196-204 [doi]
• Mitigating bitline crosstalk noise in DRAM memoriesSeyed Mohammad Seyedzadeh, Donald Kline Jr., Alex K. Jones, Rami G. Melhem. 205-216 [doi]
• Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flopsMehrdad Biglari, Dietmar Fey. 217-222 [doi]
• Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architecturesHeba Saadeldeen, Zhaoxia Deng, Timothy Sherwood, Frederic T. Chong. 223-236 [doi]
• Memory equalizer for lateral management of heterogeneous memoryChencheng Ye, Chen Ding, Hai Jin. 239-248 [doi]
• The interaction of last-level-cache mechanisms on modern processorsRakhi Hemani, Subhasis Banerjee, Apala Guha. 249-250 [doi]
• CoMerge: toward efficient data placement in shared heterogeneous memory systemsThaleia Dimitra Doudali, Ada Gavrilovska. 251-261 [doi]
• mpibind: a memory-centric affinity algorithm for hybrid applicationsEdgar A. León. 262-264 [doi]
• DRAM-related challenges in task scheduling with timing predictability on COTS multi-cores for safety-critical systemsAnkit Agrawal, Gerhard Fohler. 265-267 [doi]
• BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAMChia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi. 268-280 [doi]
• Enabling a reliable STT-MRAM main memory simulationKazi Asifuzzaman, Rommel Sanchez Verdejo, Petar Radojkovic. 283-292 [doi]
• Pagevault: securing off-chip memory using page-based authenticationBlaise-Pascal Tine, Sudhakar Yalamanchili. 293-304 [doi]
• Long short term memory based hardware prefetcher: a case studyYuan Zeng, Xiaochen Guo. 305-311 [doi]
• Task replication and control for highly parallel in-memory storesFernando Martin del Campo, Paul Chow. 312-326 [doi]
• DyAdHyTM: a low overhead dynamically adaptive hybrid transactional memory with application to large graphsMohammad A. Qayum, Abdel-Hameed A. Badawy, Jeanine Cook. 327-336 [doi]
• Rock: a framework for pruning the design space of hybrid main memory systemsDmitry Knyaginin, Per Stenström. 337-347 [doi]
• NEMO: an energy-efficient hybrid main memory system for mobile devicesBahareh Pourshirazi, Zhichun Zhu. 351-362 [doi]
• Composing lifetime enhancing techniques for non-volatile main memoriesAndrés Amaya García, René de Jong, William Wang, Stephan Diestelhorst. 363-373 [doi]
• Improving SSD lifetime with byte-addressable metadataYanqin Jin, Hung-Wei Tseng, Yannis Papakonstantinou, Steven Swanson. 374-384 [doi]
• REMAP: a reliability/endurance mechanism for advancing PCMMohammad Khavari Tavana, Amir Kavyan Ziabari, Mohammad Arjomand, Mahmut T. Kandemir, Chita R. Das, David R. Kaeli. 385-398 [doi]
• Speculative paging for future NVM storageViacheslav V. Fedorov, Jinchun Kim, Mian Qin, Paul V. Gratz, A. L. Narasimha Reddy. 399-410 [doi]
• Performance analysis for using non-volatile memory DIMMs: opportunities and challengesAmro Awad, Simon D. Hammond, Clay Hughes, Arun Rodrigues, Scott Hemmert, Robert Hoekstra. 411-420 [doi]