Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology

Jaeduk Han, Nicholas Sutardja, Yue Lu, Elad Alon. Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology. J. Solid-State Circuits, 52(12):3474-3485, 2017. [doi]

@article{HanSLA17,
  title = {Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology},
  author = {Jaeduk Han and Nicholas Sutardja and Yue Lu and Elad Alon},
  year = {2017},
  doi = {10.1109/JSSC.2017.2740268},
  url = {https://doi.org/10.1109/JSSC.2017.2740268},
  researchr = {https://researchr.org/publication/HanSLA17},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {52},
  number = {12},
  pages = {3474-3485},
}