Narender Hanchate, Nagarajan Ranganathan. A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. In 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India. pages 283-290, IEEE Computer Society, 2006. [doi]
@inproceedings{HanchateR06:2,
title = {A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise},
author = {Narender Hanchate and Nagarajan Ranganathan},
year = {2006},
doi = {10.1109/VLSID.2006.11},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2006.11},
tags = {optimization},
researchr = {https://researchr.org/publication/HanchateR06%3A2},
cites = {0},
citedby = {0},
pages = {283-290},
booktitle = {19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2502-4},
}