C. Ravi Shankar Hanuman, J. Kamala, A. R. Aruna. Implementation of high precision/low latency FP divider using Urdhva-Tiryakbhyam multiplier for SoC applications. Design Autom. for Emb. Sys., 24(2):111-125, 2020. [doi]
@article{HanumanKA20,
title = {Implementation of high precision/low latency FP divider using Urdhva-Tiryakbhyam multiplier for SoC applications},
author = {C. Ravi Shankar Hanuman and J. Kamala and A. R. Aruna},
year = {2020},
doi = {10.1007/s10617-019-09225-2},
url = {https://doi.org/10.1007/s10617-019-09225-2},
researchr = {https://researchr.org/publication/HanumanKA20},
cites = {0},
citedby = {0},
journal = {Design Autom. for Emb. Sys.},
volume = {24},
number = {2},
pages = {111-125},
}