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Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic

Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama. Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. Multiple-Valued Logic and Soft Computing, 11(5-6):619-632, 2005. [doi]

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