Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang. 15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 280-282, IEEE, 2024. [doi]
@inproceedings{HaraguchiFYCHCNWC24,
title = {15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture},
author = {Masaru Haraguchi and Yorinobu Fujino and Yoshisato Yokoyama and Ming-Hung Chang and Yu-Hao Hsu and Hong-Chen Cheng and Koji Nii and Yih Wang and Tsung-Yung Jonathan Chang},
year = {2024},
doi = {10.1109/ISSCC49657.2024.10454463},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454463},
researchr = {https://researchr.org/publication/HaraguchiFYCHCNWC24},
cites = {0},
citedby = {0},
pages = {280-282},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024},
publisher = {IEEE},
isbn = {979-8-3503-0620-0},
}