A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints

Haidar M. Harmanani, Hassan A. Salamy. A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints. International Journal of Computational Intelligence and Applications, 6(4):511-530, 2006. [doi]

Abstract

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