Hassan A. Salamy - researchr alias

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Viewing Publication 1 - 14 from 14

2022

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysisDulana Rupanetti, Hassan A. Salamy, Cheol-Hong Min, Kundan Nepal. paapp, 37(6):696-713, 2022. [doi]

2021

Thermal and energy-aware utilisation management on MPSoC architecturesDulana Rupanetti, Hassan A. Salamy. paapp, 36(5):449-469, 2021. [doi]

Energy-Aware Task Migration Through Ant-Colony Optimization for MultiprocessorsDulana Rupanetti, Hassan A. Salamy. uemcom 2021: 901-907 [doi]

Data Balanced Bagging Ensemble of Convolutional- LSTM Neural Networks for Time Series Data Classification with an Imbalanced DatasetMatthew Ward, Kevin Malmsten, Hassan A. Salamy, Cheol-Hong Min. iscas 2021: 1-5 [doi]

2020

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI ApplicationsDulana Rupanetti, Kundan Nepal, Hassan A. Salamy, Cheol-Hong Min. ccwc 2020: 228-233 [doi]

2019

Energy Efficient Scheduling with Task Migration on MPSoC ArchitecturesDulana Rupanetti, Hassan A. Salamy. eit 2019: 156-161 [doi]

Task allocation, migration and scheduling for energy-efficient real-time multiprocessor architecturesDulana Rupanetti, Hassan A. Salamy. jsa, 98:17-26, 2019. [doi]

Thermal-Constrained. Energy-Aware Load Management on MPSoC ArchitecturesDulana Rupanetti, Hassan A. Salamy. uemcom 2019: 1168-1174 [doi]

An Effective Technique to Higher Throughput for Streaming Applications on an MPSoCHassan A. Salamy. jcp, 14(8):507-518, 2019. [doi]

2013

th Root Processing EngineSemih Aslan, Hassan A. Salamy, Jafar Saniie. mwscas 2013: 1051-1054 [doi]

2012

An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock ratesHassan A. Salamy, Haidar Harmanani. mwscas 2012: 530-533 [doi]

2011

An optimal formulation for test scheduling network-on-chip using multiple clock ratesHassan A. Salamy, Haidar M. Harmanani. ccece 2011: 215-218 [doi]

2006

A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence ConstraintsHaidar M. Harmanani, Hassan A. Salamy. ijcia, 6(4):511-530, 2006. [doi]

Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic AlgorithmHaidar M. Harmanani, Hassan A. Salamy. jcsc, 15(3):331-349, 2006. [doi]

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