Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger. Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. In Dimitrios Soudris, Peter Pirsch, Erich Barke, editors, Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Volume 1918 of Lecture Notes in Computer Science, pages 118-128, Springer, 2000. [doi]
Abstract is missing.