Omar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria, Claude Thibeault. Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. In 36th IEEE VLSI Test Symposium, VTS 2018, San Francisco, CA, USA, April 22-25, 2018. pages 1-6, IEEE Computer Society, 2018. [doi]
@inproceedings{HasibCADST18,
title = {Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits},
author = {Omar Al-Terkawi Hasib and Daniel Crepeau and Thomas Awad and Andrei Dulipovici and Yvon Savaria and Claude Thibeault},
year = {2018},
doi = {10.1109/VTS.2018.8368637},
url = {http://doi.ieeecomputersociety.org/10.1109/VTS.2018.8368637},
researchr = {https://researchr.org/publication/HasibCADST18},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {36th IEEE VLSI Test Symposium, VTS 2018, San Francisco, CA, USA, April 22-25, 2018},
publisher = {IEEE Computer Society},
isbn = {978-1-5386-3774-6},
}