A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR

Tao He 0001, Michael Ashburn, Stacy Ho, Yi Zhang 0023, Gabor C. Temes. A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. In 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. pages 230-232, IEEE, 2018. [doi]

@inproceedings{HeAHZT18,
  title = {A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR},
  author = {Tao He 0001 and Michael Ashburn and Stacy Ho and Yi Zhang 0023 and Gabor C. Temes},
  year = {2018},
  doi = {10.1109/ISSCC.2018.8310268},
  url = {https://doi.org/10.1109/ISSCC.2018.8310268},
  researchr = {https://researchr.org/publication/HeAHZT18},
  cites = {0},
  citedby = {0},
  pages = {230-232},
  booktitle = {2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018},
  publisher = {IEEE},
  isbn = {978-1-5090-4940-0},
}