Yuchen He, Yunbin Luo, Yunzhengmao Wang, Tengyue Yi, Chen Jiang, Chixiao Chen, Qi Liu 0010, Ming Liu 0022, Wenning Jiang. A 16Gb/s/pin 0.51pJ/b Single-Ended NRZ Transceiver with Distributed Dual-Loop VDDQ-Ripple Compensation and Dynamic Clock Duty-Cycle Calibration for Memory Interfaces. In IEEE International Solid-State Circuits Conference, ISSCC 2026, San Francisco, CA, USA, February 15-19, 2026. pages 632-634, IEEE, 2026. [doi]
Abstract is missing.