Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems

Domenik Helms, Wolfgang Nebel. Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems. In 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007. pages 919-922, IEEE, 2007. [doi]

@inproceedings{HelmsN07,
  title = {Logic design techniques for 65 to 45nm and below for reducing total energy and solving technology variations problems},
  author = {Domenik Helms and Wolfgang Nebel},
  year = {2007},
  doi = {10.1109/ICECS.2007.4511141},
  url = {http://dx.doi.org/10.1109/ICECS.2007.4511141},
  researchr = {https://researchr.org/publication/HelmsN07},
  cites = {0},
  citedby = {0},
  pages = {919-922},
  booktitle = {14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007},
  publisher = {IEEE},
  isbn = {978-1-4244-1377-5},
}