A 32 bit 15M flop floating point programmable signal processor architecture for VLSI implementation - researchr publication authors

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James H. Hesson. A 32 bit 15M flop floating point programmable signal processor architecture for VLSI implementation. In IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '85, Tampa, Florida, USA, March 26-29, 1985. pages 196-199, IEEE, 1985. [doi]

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