James H. Hesson. A 32 bit 15M flop floating point programmable signal processor architecture for VLSI implementation. In IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '85, Tampa, Florida, USA, March 26-29, 1985. pages 196-199, IEEE, 1985. [doi]
@inproceedings{Hesson85,
title = {A 32 bit 15M flop floating point programmable signal processor architecture for VLSI implementation},
author = {James H. Hesson},
year = {1985},
doi = {10.1109/ICASSP.1985.1168480},
url = {https://doi.org/10.1109/ICASSP.1985.1168480},
researchr = {https://researchr.org/publication/Hesson85},
cites = {0},
citedby = {0},
pages = {196-199},
booktitle = {IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '85, Tampa, Florida, USA, March 26-29, 1985},
publisher = {IEEE},
}